Die ontwikkeling en evaluering van 'n 8DPSK trelliskode datasender en ontvanger

Abstract

A large increase in the demand for data transmission in its various forms has led to the viewpoint that the second half of the twentieth century is regarded as the era of evolution for digital communication. This thesis explores the use of the trellis code modulation with differential phase-shift keying as modulation technique in a half-duplex modem configuration. The transmitter was initially designed to operate at a data rate of 3200 bits per second, but as a result of problems with processing time in the receiver the data rate of the whole system was down-graded to 1066 bits per second. The bandwidth of the system was also scaled down accordingly. Trellis code modulation was chosen for the modulation process because of its error correcting and other features with respect to phase-shift keying (PSK). This advantage is obtained without any loss of data rate, or increase in bandwidth requirements because with trellis code modulation data-encoding and modulation are a single technique. Decoding of the trellis code at the receiver is accomplished with a Viterbi decoder to take maximum advantage of the process of trellis code modulation. Development of the system was preceded by mathematical simulations of the transmitter and receiver, and this largely contributed to the determination and avoidance of problems. Mathematical simulations played a vital role in the ultimate implementation of the system in digital architecture. The transmitter and receiver were based on the use of the Peralex SIG56 card with the Motorola DSP 56001 processor while the TLC32044 converter was used for all the digitising and filtering processes. The transmitter was evaluated in terms of the frequency spectrum and constellation of the transmitted signal. It was found that the transmitter was reasonably stable with respect to generation of the required phase shifts and the frequency spectrum of the output signal fell within the predicted frequency range. Measurements were made of the bit error rate with regard to the signal-to-noise ratio to determine the performance of the receiver. The receiver was first evaluated by determining its performance with the DSPK modulation process. After this the entire receiver was evaluated, including the Viterbi decoding process. In both cases it was found that performance of the process/techniques were very close to the theoretical values (typically 2dB to 3dB poorer). Satisfactory operation ceased at a signal to noise energy ratio of ± 15dB as a result of the synchronous detector not being able to maintain synchronisation. During execution of the project insight was gained with respect to the following: • Trellis code modulation and the use of convolution codes in general. • Use of DSP in a personal computer environment. The integration of software used in the personal computer and the DSP 56001 was illuminating. • The implementation of the Viterbi decoding algorithm in DSP. • Symbol synchronisation and the use of a correlation detector.